Memory access delays?

[MarathonMan]

Anyone have any idea how many cycles it takes to write to memory mapped registers (roughly)? Does the VR4300 just have to synchronize to the RCP bus clock and the memory-mapped registers will capture the value immediately, or is there some delay involved like RAM?

I'm guessing I'll need the actual hardware to determine something like this...

 

[zoinkity]

Here's a graph of the RSP DMA rate courtesy of Halley's Comet Software.
http://hcs64.com/dma.html

The rate differs on an iQue (a tad quicker), but wouldn't know by how much.

DMA can only occur to hardware addresses, so address translation occurs before the transfer is set. Obviously playing with the cache settings or TLB lookup is a matter of implementation.