BDMEmu - Bandai Design Master emulator v1.0 released!

Bandai Design Master bootstrap emulator

This is a small C11 emulator for the Bandai Design Master / Denshi Mangajuku that can run on the Web or natively for Qt6/Linux or Windows with Win32 backend.

Current scope:

• Hitachi H8/300-style 16-bit CPU interpreter with enough instructions to leave reset, run the common cartridge startup paths, execute the observed bank-switch thunk, service the timer interrupt path, read touch ADC data, and reach the Dragon Ball Z title/mode menu.
• MAME-derived base map: cartridge window at 0x0000-0x7fff, external SRAM from 0x8000-0xfb7f, H8-family internal RAM at 0xfb80-0xff7f, and high I/O at 0xff80-0xffff.
• Headless frontend.
• Opaque handles for core, video, input, and sound.
• Tentative H8 timer-derived sound backend with optional mono 16-bit PCM WAV recording.
• H8/3334 peripheral model improvements:
  • Timer16 register layout from MAME's H83337 map: 0xff90 TIER, 0xff91 TSR, 0xff92-0xff93 TCNT, 0xff94-0xff95 observed OCRA, and 0xff96 TCR. The regular UI/startup interrupt now comes from the modeled counter/compare path rather than a separate artificial interval counter.
  • Timer8 channel register shadows and counters at 0xffc8-0xffcc and 0xffd0-0xffd4; these feed the sound backend and make timer status/counter reads deterministic.
  • SCI status reads at 0xff8c/0xffdc return transmitter-ready state, which is closer to the H8 reset behavior than returning the raw erased I/O byte.
  • Port 6 data writes at 0xffbb are tracked as resistive-panel drive state for ADC sampling.
• LCD model for the interface touched by the games:
  • 0xff80 is treated as LCD/gate-array register index.
  • 0xff81 is treated as LCD/gate-array register data.
  • The observed initialization writes register 0x12 = 0x14 and 0x14 = 0x77, matching a 20-byte stride and 120 active scanlines.
  • The first 0x960 bytes of SRAM at 0x8000-0x895f are mapped as a 160x120 1bpp framebuffer, MSB-first, and exported as a 160x120 frame.
• G-cart bank-latch model:
  • Writes to 0xff84 update ROM bank A15/A16 using the low two bits.
  • This matches the copied RAM thunk used by G.01/G.02/G.03: write bank, delay, then JSR 0x0000; nonzero banks contain JMP vectors at offset zero.
  • Bit 2 is reserved as a tentative media-cart select when --media is loaded.
• Deterministic port-7/gate-array input placeholder:
  • 0xffbe returns port 7.
  • Bit 7 is kept high as the observed ready/handshake input.
  • Bit 4 defaults low as the active-low battery/sense line needed by the startup path.
  • The documented A/B/C/D/E menu strip and left/right page controls are modeled as touch-panel locations, not as controller-style P7 bits. Frontends map keyboard/gamepad buttons to stylus taps at those panel coordinates.
  • --port7 HEX remains available for exact override/fuzzing.
• H8 ADC model for the resistive touch panel:
  • 0xffe0-0xffe7 expose four 10-bit sample registers in H8 format.
  • 0xffe8 is ADCSR and starts a short delayed conversion when ADST is set.
  • 0xffe9 is ADCR.
  • Channels 0/1 model the panel vertical voltage; channels 2/3 model horizontal voltage. This channel order is required by the cartridge calibration math.
  • Port-6 drive values 0x0c, 0x09, and 0x06 now affect whether the sampled raw or complementary panel axis is returned, instead of ignoring the electrode drive state completely.
• Additional H8 coverage for the boot and graphics paths, including register-indirect JSR @Rn, memory/absolute bit operations, register ADDX.B, byte DIVXU, and corrected byte shift/rotate decoding for SHLR, SHAR, ROTXL, ROTL, ROTXR, and ROTR.
• Raw cartridge graphics preview mode for verifying that cartridge 1bpp art can pass through the LCD renderer.
• Whole-machine save states through the core API, shared by headless, SDL 1.2, SDL3, Qt6, Win32/Win64, and WASM. State files include CPU registers/flags/PC, internal/external RAM, LCD registers/VRAM/framebuffer state, fixed-point input/touch state, H8 timer/ADC shadows, cart/media bank state, and sound timer/noise/phase state. ROM bytes are not embedded, so load the same G/M/BIOS images before loading a state. The save-state format is intentionally not backward compatible; after the panel-button rewrite, old .bdmst files are rejected instead of translated.

Not implemented yet:

• Cycle-perfect H8/328/329 peripheral timing.
• Complete custom HG62G010 gate-array behavior.
• Confirmed media-cart CE/clock behavior.
• Exact nonvolatile drawing/media-cart RAM semantics. External SRAM can now be loaded/saved, but retention, battery state, and media-destructive-use behavior are not unknown.
• Full H8 opcode coverage.
• Compare this against real hardware in much more details than what i can do

This is a working, Bandai Design Master emulator. It has sound support, and can boot into the games. (the games were dumped in 2020 by the Gaming Alexandria).
This is the first emulator to being able to do so, as MAME is currently not able to emulate this console properly, and lacks sound support for it.

GitHub - gameblabla/BDMEmu: Bandai Design Master emulator, for Windows/Linux/Web

Bandai Design Master emulator, for Windows/Linux/Web - gameblabla/BDMEmu

github.com