The union looks fine, but keep in mind a Word is 32bits (well, on most systems), and 2 bytes is only 16. So for that to work, you'd have to map 4 bytes in that switch, or two 2byte switches in a switch within the union. As for a risc interpreter on x86 - why not? What else would you write it on, a MAC?
Here's a crash course in RISC arcitecture emulation- (using PPC as an example)
Unlike CISC, where opcodes are of variable size, and can be identified simply by a one or 2 byte field, RISC is as you know fixed length opcodes, usually 32bit. Take a pseudo PPC opcode:
--------------32 Bits----------------------------------------------
[Bits 0-5][Bits 6-10][Bits 11-15][Bits 16-20][Bits 21-30][Bit 31]
As you know, it's divided up into sections (PPC is big endian btw). In this example, the first 6 bits, 0-5, are the opcode identifier, which has a possible range from zero to 64. Each identifier specifies an instruction, or, in some cases, a branch to other instructions. So, a simple way to do this, would be to do:
Code:
switch((opcode >> 26)&0x3F)
{
case 0: Opcode_NOP(); break;
case 1: Opcode_OR(); break;
...
case 31: Opcode_31(); break;
In this case, the value of 31 has multiple opcodes, so you'd call a function with another switch, and this time, check the opcode extension. On PPC, this extension is bits 21-30. It's probably different on the cpu your emulating. So, just do switch((opcode >> 1)&0x3FF).
Tada... instruction decoding on RISC, no strings attached. It's really very easy to do an interpreter like this. Now, take the other sections. Bits 6-10, 11-15, and 16-20 are register fields in this example. Thus, each field represents a value of the GPR to manipulate by the instruction. In this example, the first would be REGD, the second REGA, and the third REGC. Each is 5 bits, thus can have a value from 0-31, which points to one of the PPC's 32 general purpose registers, respectivly. Here's a pseudo op:
In your cpu manual, it might say something like this:
Opcode: MUL
regDest = regSrcA * regSrcB
Now, in C++:
Code:
void Opcode_MUL(u32 opcode)
{
reg.gpr[(opcode>>21)&0x1F] = reg.gpr[(opcode>>16)&0x1F] * reg.gpr[(opcode>>11)&0x1F] ;
}
A good tip is to use macros for all that shifting, ie #define REG_D ([(opcode>>21)&0x1F) - so you are less prone to making mistakes. As for Bit31, it could be on anything, on PPC though it's a flag called Rc to calculate a field of the CR register.
There you have it. As for most of the other parts, it acts pretty much in the same nature as a CISC processor, to an extent. Hope that helps a little
